I think the timing is about right … we’ve been using DDR4 desktop DRAM for quite a while now. With 7nm becoming the norm in 2020, it’s only a matter of time before we see DDR5 desktop DRAM/DIMMs real soon.
Taken from Cadence … I talked recently to Marc Greenberg, one of Cadence’s experts on the memory market. Despite the fact that the JEDEC DDR5 standard is still under development, Marc says that: 2020 will be the year of DDR5.
He is excited about it since a new DRAM only comes around every 8-10 years. We had our first DDR5 7nm testchips in silicon almost two years ago, and since then we’ve repeated that in multiple foundries and nodes.
This is another first in terms of DDR IP:
- World’s first DDR5 7nm silicon IP
- World’s first GDDR6 7nm silicon IP
- World’s first LPDDR5 7nm silicon IP
The photograph shows the Cadence DDR5 test board.
In fact, back in May 2018, I wrote about how our preliminary DDR5 IP was operating successfully with Micron’s preliminary DDR5 DRAM chips. For details, see my post DDR5 Is on Our Doorstep. That was nearly two years ago. It is still on our doorstep, in the sense that JEDEC has not published the official standard. But it is also on our doorstep in the sense that IP and memories are available, and systems are being designed around them.
I asked him how we could create test chips when the standard is not even out:
Close participation in the JEDEC working groups is an advantage. We get insight into how the standard will develop. We are a controller and PHY vendor and can anticipate any potential changes on the way to final standardization. In the early days of the standardization, we were able to adopt standard elements under development and work together with our partners to get very early working silicon. As we approach the release of the standard, we get more proof points to indicate that our IP will support DDR5 devices compliant to the standard.
Read the rest over at Cadence
